/**************************************************************************//**
 * @file     pan_phy.c
 * @version  V1.00
 * $Date: 20/12/14 9:39a $
 * @brief    Panchip private rf driver source file
 *
 * @note
 * Copyright (C) 2020 Panchip Technology Corp. All rights reserved.
 *****************************************************************************/
 
#include "PanSeries.h"
#include "pan_phy.h"
#include "pan_pri_rf.h"
#include "pan_sys.h"
//#include "comm_prf.h"

#if 0
#define NORDIC170                                   0
#define BOE2                                        0
#define RSSI_DET_CONTI_UP                           1
#define PREAMBLE_OFFSET_CLR                         1
#define MODE_250KBPS                                1
#define MODE_1MBPS                                  1
#define MODE_2MBPS                                  1
#define MODE_LR                                     0
#define LOW_GAIN                                    1
#define CPM_DEMOD																		0
// <o> AGC Mode
//  <0=> Default
//  <1=> New Version
//  <2=> Force Gain
// <i> Selects AGC Mode
#define CFG_RF_PHY_AGC_MODE                         2

// <o> TX Power
//  <1=> 0 dBm
//  <3=> 6 dBm
//  <4=> 10 dBm
// <i> Selects TX Power
#define CFG_RF_PHY_TX_POWER                         4

// <o> PLL & VCO Calibration
//  <0=> Original
//  <1=> New Version
// <i> Selects TX Power
#define CFG_VCO_PLLBW_CALIB_MODE                    0

// <e> AGC Time Settings
//  <i> Useful only if `AGC Mode = Default`
#define CFG_AGC_TIME_SETTINGS_ENABLE                1

//   <o> AGC Iter Wait Time
//    <0x0016=> 0.6825us (original)
//    <0x0020=> 1us
//    <0x0040=> 2us
//    <0x0060=> 3us
//    <0x0080=> 4us
//    <0x00A0=> 5us (default)
//    <0x00C0=> 6us
//   <i> R0097[4:0] wait_time[12:8]
//   <i> R0098[7:0] wait time[7:0]
//#define CFG_ITER_TIME                               0x0030
#define CFG_ITER_TIME                               0x0002

//   <o> AGC Switch Delay
//    <0x20=> 1us
//    <0x40=> 2us
//    <0x60=> 3us (default)
//    <0x80=> 4us
//    <0xA0=> 5us
//    <0xC0=> 6us
//   <i> R008C[7:0] wait_time_switch[7:0]
#define CFG_AGC_SWITCH_DELAY                        0x40
//#define CFG_AGC_SWITCH_DELAY                        0x60

// </e>


//   <o> IQ Scale Delay
//    <0x01=> 0.25us (original)
//    <0x05=> 1.25us
//    <0x0A=> 2.5us
//    <0x0F=> 3.75us
//    <0x14=> 5us (default)
//    <0x19=> 6.25us
//    <0x1E=> 7.5us
//    <0x23=> 8.75us
//    <0x28=> 10us
//    <0x2D=> 11.25us
//    <0x32=> 12.5us
//    <0x37=> 13.75us
//    <0x3C=> 15us
//   <i> R00BF[5:0] demod_iq_scale_delay
#define CFG_IQ_SCALE_DELAY                          0x0A

//   <o> IQ Switch Delay
//    <0x12=> 1us
//    <0x22=> 2us (original)
//    <0x2A=> 2.5us
//    <0x32=> 3us
//    <0x52=> 4us (default)
//    <0x62=> 5us
//    <0x72=> 6us
//    <0x82=> 7us
//   <i> R00D4[7:2] AGC gain switch timeout
//   <i> R00D4[1:0] Rssi data source select
#define CFG_IQ_SWITCH_DELAY                         0x22

//   <o> TX Power
//    <1=> 0 dBm        <3=> 6 dBm
//    <4=> 10 dBm
//    <i> Selects TX Power
#define CFG_RF_PHY_TX_POWER                         4

const uint32_t init_sleep[] =
{
	0x001900B0
};

const uint32_t init_stdby_config[] =
{
    0x0A0000A0,
    0x0A0100A0,
    0x781100A0,
    0x011300A0,
    0x021B00B0
};

const uint32_t init_slp_to_stdby_config[] =
{
    0x001B00B0
};

const uint32_t pwr_reset[] =
{
    0x0A00E004,
    0x0A03E014  // set pwr_mag_stdbyen & ioring_rst_n
};

const uint32_t phy_init[] =
{
	 /* 1 Parameters Initialization */
    0x0000FF02, /* select Page 0 */
    
    /* 1.1 PLL/VCO/PA/RXFilter etc. */
    0x000C7802, /** 
                 * <7:6>: Reserved                      = 0
                 * <5:3>: FSYN/VCO varactor bias(extra) = 3
                 * <2:0>: NMOS bias(original)           = 0
                 */
    0x00037902, /**
                 * <7>  : FSYN/VCO varactor bias short = 0
                 * <6>  : FSYN/VCO NMOS bias short     = 0
                 * <5>  : FSYN/VCO tail bias short     = 0
                 * <4:2>: Reserved                     = 0
                 * <1:0>: RX offset trim               = 3
                 */
    0x00147A02, /**
                 * <7:5>: PA mode        = 0 (off)
                 * <4>  : RX IQ switch   = 1
                 * <3>  : PA cap short   = 0 (slow ramp)
                 * <2:> : RX/Filter bias = 1 (high current)
                 * <1:0>: RXIF test mode = 0 (no input/output)
                 */

    0x0A0E7002, /**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 0 (PA CORE disable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b10
                 */
    
//    0x00022802, 
                /**
                 * <7:2>: Reserved        = 0
                 * <1>  : rfmtchntwklnaen = 1
                 * <0>  : rfmtchntwkpaen  = 0
                 */
    0x00056202, /**
                 * <7>  : Reserved   = 0
                 * <6:3>: Reserved   = 0
                 * <2:0>: rxlnaicore = b101 (477mV)
                 */
    0x00206602, /**
                 * <7>  : rxmxren   = 0 (RXMXR disable)
                 * <6:4>: rxmxrcm   = b010 (543mV, Bias option for RXMXR Vcm)
                 * <3:0>: Reserved  = 0
                 */
    /* 1.2 MODEM */
    0x0000BF02 | (CFG_IQ_SCALE_DELAY << 16),
    0x00027E02,

    /* DEMOD */
    0x00A0C202,//[0]:wide_bw_mode(default:0xA0 option:0xA1)    need to replace all 
    //offset-estimation
    0x0000D502,//reduce preamble(default:0x00 option:0x33)
    //frequancy-det
    0x0005DF02,
#if BOE2  //disable eq
    0x0007DE02,
#else
    0x0057DE02,
#endif
     0x0014C402,
//			0x0000dd02,// max
//			0x0000C402,// min
//			0x0000C502,// similiar
//0x0042f002,
//0x0033d502,

//

    0x0009C102,
    0x0079D302,//[1:0]  rssi-cal-src  00: ply-phs 0x007AD302
		           //01:cmplx-fltr
		           //10:adc
		           //11:acg
    //iq-scale
    0x000DF102,//iq-scale value (default:0x0d option:0x10)
    0x0000D402 | (CFG_IQ_SWITCH_DELAY << 16),

    /* 1.3 AGC & RSSI */

//    0x00889002, /**
		0x00899002, /**
                 * <7>  : aggressive_cdr   = 1
                 * <6>  : iteration_freeze = 0//cannot set 1 
                 * <5:2>: iteration_limit  = 2(00_10)
                 * <1>  : switch_freeze    = 0
                 * <0>  : switch_tmr_en    = 0
                 */


    0x00009702 | (((CFG_ITER_TIME >> 8) & 0xFF) << 16),
    0x00009802 | (((CFG_ITER_TIME >> 0) & 0xFF) << 16),
    0x00008C02 | (CFG_AGC_SWITCH_DELAY << 16),
    0x00058D02,//switch-cnt	(default:0x01 option:0x03)
//		0x00018D02,//switch-cnt	(default:0x01 option:0x03)


//-------------------------
// AGC default version
//-------------------------	
    0x009BA202,//scale_th=-101dbm
    0x0006A302,
    0x0007A302,
    0x0006A302,
    0x0000A302,
		
    0x0006A202,//hys = 4
    0x000aA302,
    0x000bA302,
    0x000aA302,
    0x0000A302,
#if LOW_GAIN		
    //Rssi_th  
//    0x00EAa202,//th1=-22
//    0x00bfa202,//th2=-65
//		0x00cea202,//th1=-50
//		0x00c9a202,//th1=-55
//    0x00c4a202,//th1=-60
//		0x00cda202,//th1=-51
    0x00DFa202,//th1=-33
//    0x00D8a202,//th1=-40
    0x0000a302,
    0x0001a302,
    0x0000a302,
//    0x00DFa202,//th1=-33
//		0x00b9a202,//th3=-71
//		0x00b2a202,//th2=-77
//		0x00b0a202,//th2=-80
    0x00cda202,//th1=-51
//    0x00bfa202,//th1=-65
    0x0002a302,
    0x0003a302,
    0x0002a302,
		0x00b9a202,//th3=-71
//    0x00D8a202,//th1=-40
//    0x00aba202,//th3=-85
//		0x00b3a202,//th3=-77
//		0x00b2a202,//th3=-78
//		0x00b0a202,//th3=-80		
    0x0004a302,
    0x0005a302,
    0x0004a302,
    //FIX      
    0x000Ea202,//fix0
    0x000ca302,
    0x000da302,
    0x000ca302,
    0x00FCa202,//fix1
    0x000ea302,
    0x000fa302,
    0x000ea302,
    0x00EAa202,//fix2
    0x0010a302,
    0x0011a302,
    0x0010a302,
		0x00D6a202,//fix3
    0x0012a302,
    0x0013a302,
    0x0012a302,
	
    0x0000a202,//Gain_word0
    0x0014a302,
    0x0015a302,
    0x0014a302,
    0x0001a202, //Gain_word1   
    0x0016a302,
    0x0017a302,
    0x0016a302,
    0x000ba202,//Gain_word2
    0x0018a302,
    0x0019a302,
    0x0018a302,
    0x0013a202, //Gain_word3    
    0x001aa302,
    0x001ba302,
    0x001aa302,	
#else
 //Rssi_th  
//    0x00EAa202,//th1=-22
//    0x00bfa202,//th2=-65
//		0x00cea202,//th1=-50
//		0x00c9a202,//th1=-55
//    0x00c4a202,//th1=-60
//		0x00cda202,//th1=-51
//    0x00DFa202,//th1=-33
    0x00D8a202,//th1=-40
    0x0000a302,
    0x0001a302,
    0x0000a302,
//    0x00DFa202,//th1=-33
//		0x00b9a202,//th3=-71
//		0x00b2a202,//th2=-77
//		0x00b0a202,//th2=-80
//    0x00cda202,//th1=-51
    0x00bfa202,//th1=-65
    0x0002a302,
    0x0003a302,
    0x0002a302,
//		0x00b9a202,//th3=-71
//    0x00D8a202,//th1=-40
//    0x00aba202,//th3=-85
//		0x00b3a202,//th3=-77
		0x00b2a202,//th3=-78
//		0x00b0a202,//th3=-80		
    0x0004a302,
    0x0005a302,
    0x0004a302,
    //FIX      
    0x0007a202,//fix0
    0x000ca302,
    0x000da302,
    0x000ca302,
    0x00F5a202,//fix1
    0x000ea302,
    0x000fa302,
    0x000ea302,
    0x00DCa202,//fix2
    0x0010a302,
    0x0011a302,
    0x0010a302,
		0x00CFa202,//fix3
    0x0012a302,
    0x0013a302,
    0x0012a302,
	
    0x0004a202,//Gain_word0
    0x0014a302,
    0x0015a302,
    0x0014a302,
    0x0005a202, //Gain_word1   
    0x0016a302,
    0x0017a302,
    0x0016a302,
    0x000fa202,//Gain_word2
    0x0018a302,
    0x0019a302,
    0x0018a302,
    0x0017a202, //Gain_word3    
    0x001aa302,
    0x001ba302,
    0x001aa302,	
#endif
    0x00aca202, //conv_gain    
    0x001ca302,
    0x001da302,
    0x001ca302,	
//-----------------------  AGC end -------------------------------	
    //1M  preamble
    //gain
    0x0000DA02,  //0x0000DA02
    0x007CDB02,  //0x005CDB02
    0x0010D902,
    0x0011D902,
    0x0010D902,
    0x0000DA02,
    0x0035DB02,
    0x0012D902,
    0x0013D902,
    0x0012D902,
    0x00E0DA02,
    0x00CFDB02,
    0x0014D902,
    0x0015D902,
    0x0014D902,
    //b1
    0x00C5DA02,  //0x00C6DA02
    0x0006DB02,  //0x0076DB02
    0x0016D902,
    0x0017D902,
    0x0016D902,
    0x00E1DA02,
    0x00D0DB02,
    0x0018D902,
    0x0019D902,
    0x0018D902,
    //b2
    0x001BDA02, //0x0019DA02
    0x0043DB02, //0x00E9DB02
    0x001AD902,
    0x001BD902,
    0x001AD902,
    0x00F4DA02,
    0x0040DB02,
    0x001CD902,
    0x001DD902,
    0x001CD902,

    //2M preamble
    //gain
    0x0005DA02,  //0x0001DA02
    0x003DDB02,  //0x003FDB02
    0x0020D902,
    0x0021D902,
    0x0020D902,
    0x00FFDA02,
    0x00CBDB02,
    0x0022D902,
    0x0023D902,
    0x0022D902,
    0x00E0DA02,
    0x007BDB02,
    0x0024D902,
    0x0025D902,
    0x0024D902,
    //b1
    0x00C2DA02,  //0x00C2DA02
    0x000DDB02,  //0x000CDB02
    0x0026D902,
    0x0027D902,
    0x0026D902,
    0x00E1DA02,
    0x0062DB02,
    0x0028D902,
    0x0029D902,
    0x0028D902,
    //b2
    0x001EDA02,  //0x001EDA02
    0x0000DB02,  //0x0001DB02
    0x002AD902,
    0x002BD902,
    0x002AD902,
    0x00ECDA02,
    0x0080DB02,
    0x002CD902,
    0x002DD902,
    0x002CD902,
    // end
    // AGC default
    0x00007902,//[4]:internal sd-clk [3]:cob-sd_clk
                 //[3]: force gain
//		           //[2:0]: force gain-idx
    0x00019502, /** 
                 * <7:5>: Reserved              = 0
                 * <4>  :
                 * <3>  : cntrl_force_gain      = 0
                 * <2>  : agc_en_sel            = 0
                 * <1>  : agc_en_ovrd           = 0
                 * <0>  : freeze                = 1 (when access_address matches, agc is locked)
                 */
#if RSSI_DET_CONTI_UP
	  0x0046c902, /**      0100_0110 = 46
		             * <7  >:  Resolution  0:1db   1:0.25db
								 * <6  >:  SW_Rssi_gap_Enable  
                 * <5  >:  rssi_Gap det-time  :0:2us 1:4us
								 * <4:2>:  RSSI_GAP  (db*4)   
								 * <1:0>: tx-data_src           = 10
								 */
#else
	  0x0006c902, /**      0000_0110 = 06
		             * <7  >:  Resolution  0:1db   1:0.25db
								 * <6  >:  SW_Rssi_gap_Enable  
                 * <5  >:  rssi_Gap det-time  :0:2us 1:4us
								 * <4:2>:  RSSI_GAP  (db*4)   
								 * <1:0>: tx-data_src           = 10
								 */
#endif
    //			0x0000dd02,  //similiar peak-though
#if PREAMBLE_OFFSET_CLR
	#if MODE_2MBPS
		0x00483b02,
	#else
    0x004b3b02,/* 0100_0011  0x00543b02
		              [6] preamble ofstEst clear en	
							    [5:0]  preamble ofstEst Hold Time : (N+1)*2
							 */
	#endif
    0x00013c02,/* [4] offset Delay 4us
		              [3:0] default 0001
								*/
#else
    0x00033b02,/* 0000_0011 
		              [6] preamble ofstEst clear en	
							    [5:0]  preamble ofstEst Hold Time : (N+1)*2
							 */			
    0x00013c02,/* [4] offset Delay 4us
		              [3:0] default 0001
								*/							 
#endif
               
    0x0000D402 | (CFG_IQ_SWITCH_DELAY << 16),
    0x003d4e02,//Force agc gain idx  20   [4:2] idx   [0] force
		0x004a2c02,//iq-swap
		

    
//////		0x000caf02,//rssi-result avg
    0x00807b02,//gain_idx
//    0x000e7902,//
//		0x00002802,//

		
//	 // DEV =  175K (pre_rx)
//	  0x0006C102, //[5:0]:DFE fb-coef
//    0x0050d302, //[7:3]:DFE ff-coef
//    0x0003df02, //[3:0]:DFE ff-th
//    0x0035de02, //[7:4]:FFE coeff 
//		            //[3:0]:FFE th

// 	//DEV = 175K (pre_tx) scale factor
//	  0x0000C602,//  default:{C6,C7,C8} = 0x010000,  dev = 250K
//    0x00A3C702,//
//    0x00D7C802,//  

////////res-dcoc idx=4
//////0x00030002,
//////0x00003e02,
//////0x00a73f02,//i -167
//////0x00034e02,
//////0x00df4f02,//q +33
//////0x0000ff02,

//---------------------------		
#if	CPM_DEMOD
	
		// cpm xcorr-reg config
		0x0000ff02,
		0x00089902,
//		0x00809902,		
//		0x00379902,		
//		0x00779a02, // [3]=>0:long buf, 1:short buf; [2]=>1:xcorr from reg, 0:xcorr from auto; [1]=>dagc_en; [0]=>codemod_en
		0x00529a02, // coherent-demod Off	
//		0x00469b02, // [7:4]=>fakeTh
		0x00b69b02,
		0x00029c02,  // [7:0]=>sumTh
		0x00649d02,
		0x00069e02,
		0x00469f02,
		0x00aaa002,
		0x00c0a102,
		0x00eaa402,
		0x00a4a502,
		0x0000a602,
		0x00eaa702,
		0x00aaa802,

////		// cpm xcorr-autogen config, Plan#1
//		0x0000ff02,
//		0x00089902,
//		0x00739a02, // [3]=>0:long buf, 1:short buf; [2]=>1:xcorr from reg, 0:xcorr from auto; [1]=>dagc_en; [0]=>codemod_en
////		0x00a69b02, // [7:4]=>fakeTh
//		0x00b69b02, // [7:4]=>fakeTh
//		0x00029c02,  // [7:0]=>sumTh
//		0x0071a402,  //syncword msb
//		0x0076a502,  //syncword
//		0x0041a602,  //syncword
//		0x0029a702,  //syncword lsb	
//		0x0001a802,
//		
////		// cpm xcorr-autogen config, Plan#2
//		0x0000ff02,
//		0x00089902,
//		0x006b9a02, // [3]=>0:long buf, 1:short buf; [2]=>1:xcorr from reg, 0:xcorr from auto; [1]=>dagc_en; [0]=>codemod_en
////		0x00a69b02, // [7:4]=>fakeTh
//		0x00a69b02, // [7:4]=>fakeTh
//		0x00029c02,  // [7:0]=>sumTh
//		0x0076a402,  //syncword msb
//		0x0041a502,  //syncword
//		0x0029a602,  //syncword
//		0x0055a702,  //syncword lsb		
//		0x0001a802,

#else
			0x00529a02, // coherent-demod Off	
			0x00089902,
#endif

//// for test new dagc
//// before r357
////		0x00282A02, //dagc_en, don't use now
//		0x0001F102,  //target
//		0x0013F402,  //alph1
//		0x00402a02,  //alph2
//		0x0000bf02,  //dagc_manual_en
//		0x0004d402,  //dagc_manual_value

// after r357
		//		0x00282A02, //dagc_en, don't use now
		0x0016F402,  //alph1=>[3:0]
		0x0002F102,  //alph2=>[3:0]
		0x0006bf02,  //int alph1 =>[3:0]
		0x00202a02,  //int alph2=>[7:4], manu_en=>[3]
		0x0022d402,  //para sw th=>{[7:2],2'b0}
//		0x001bF402,  //alph1=>[3:0]
//		0x0004F102,  //alph2=>[3:0]
//		0x000bbf02,  //int alph1 =>[3:0]
//		0x00402a02,  //int alph2=>[7:4], manu_en=>[3]
//		0x0012d402,  //para sw th=>{[7:2],2'b0}

//		0x0040a102, 
//		0x0008a002, 
////// for test new dagc end

//		0x0004c002,  // preamble th
//---------------------------		
		0x00338302, //[2:0]=>mode_forAGC, [6:4]=>mode_forRSSI;
		0x00208402, //[5:0]=>coeff_forAGC, y=coeff*y+(1-coeff)*x
//		0x00088402, //[5:0]=>coeff_forAGC, y=coeff*y+(1-coeff)*x
		0x0c0C7F02, //[7:2]=>coeff_forRSSI, y=coeff*y+(1-coeff)*x
		//0x00407F02, //[7:2]=>coeff_forRSSI, y=coeff*y+(1-coeff)*x
		0x0080af02, // Disable avg, [7]=>dagc_mode:1->dagc,0->rssi_dagc
//#if BOE2							 
//     0x00201002,//drift_compensate zcones_offset  0: >>0   1:>>1   2:>>2
//		 0x00c01102,//drift_compensate zcNormal       default :96(dec)
//#else
//     0x00001002,
//		 0x00c01102,
//#endif
#if BOE2							 
		0x00201002,//[1:0] zcnormal_shift : 0:>>>0     1: >>>1    2:>>>2
		0x00f21102,//[7:1]   default value = 7'h60 (96-dec)
		0x00206a02,//[7:3]   zcones_scale_factor
#elif NORDIC170
     0x00001002,
		 0x00d21102,
		 0x005C6a02,//[7:3]   zcones_scale_factor
#else
		0x00001002,//[1:0] zcnormal_shift : 0:>>>0     1: >>>1    2:>>>2
		0x00c01102,////[7:1]   default value = 7'h60 (96-dec)
#endif
		0x00b09302,	 // s2s8 sum th
//
    0x0001ff02,
		//0x00af2002,//[7:0]:s2s8 offset-timeout     * 2
		0x00322002,//[7:0]:s2s8 offset-timeout     * 2
		//0x00562102,//[7:0]:zc_difference_scale[8:1]
//		0x007f2102,//[7:0]:zc_difference_scale[8:1]
    0x00882202,//[7]:zc_difference_scale[0]
		           //[3]:s2s8_preamble_corr_cnt_en
							 //[2:0]:s2s8_preamble_corr_cnt_th
		//0x00182302,//[7:0]:s2s8 chip_cnt_th
//		0x00102302,//[7:0]:s2s8 chip_cnt_th
		0x001a9f02,//avg off
    0x00025602,//notch off
//		0x001b9f02,//avg on
//    0x00065602,//notch on	
		0x003e1e02, //preamble_found,rssi th
		0x00e81f02,	
    0x0000ff02,
#if BOE2
    0x0000d602,//0
    0x0000d702,
    0x0001d802,
    0x0005d802,
    0x0001d802,
    0x0000d602,//1
    0x0000d702,
    0x0009d802,
    0x000Dd802,
    0x0009d802,
    0x0000d602,//2
    0x0000d702,
    0x0011d802,
    0x0015d802,
    0x0011d802,
    0x0000d602,//3
    0x0000d702,
    0x0019d802,
    0x001Dd802,
    0x0019d802,
    0x0000d602,//4
    0x0000d702,
    0x0021d802,
    0x0025d802,
    0x0021d802,
    0x0000d602,//5
    0x0000d702,
    0x0029d802,
    0x002Dd802,
    0x0029d802,
    0x0002d602,//6
    0x00C0d702,
    0x0031d802,
    0x0035d802,
    0x0031d802,
    0x0003d602,//7
    0x0000d702,
    0x0039d802,
    0x003Dd802,
    0x0039d802,
    0x0003d602,//8
    0x0000d702,
    0x0041d802,
    0x0045d802,
    0x0041d802,
    0x0003d602,//9
    0x0000d702,
    0x0049d802,
    0x004Dd802,
    0x0049d802,
    0x0002d602,//10
    0x0000d702,
    0x0051d802,
    0x0055d802,
    0x0051d802,
    0x0001d602,//11
    0x0080d702,
    0x0059d802,
    0x005Dd802,
    0x0059d802,
    0x00FEd602,//12
    0x0080d702,
    0x0061d802,
    0x0065d802,
    0x0061d802,
    0x0000d602,//13
    0x0000d702,
    0x0069d802,
    0x006Dd802,
    0x0069d802,
    0x0000d602,//14
    0x0000d702,
    0x0071d802,
    0x0075d802,
    0x0071d802,
    0x0000d602,//15
    0x0000d702,
    0x0079d802,
    0x007Dd802,
    0x0079d802,
    0x0000d602,//16
    0x0000d702,
    0x0081d802,
    0x0085d802,
    0x0081d802,
    0x0000d602,//17
    0x0000d702,
    0x0089d802,
    0x008Dd802,
    0x0089d802,
    0x0000d602,//18
    0x0000d702,
    0x0091d802,
    0x0095d802,
    0x0091d802,
    0x0000d602,//19
    0x0000d702,
    0x0099d802,
    0x009Dd802,
    0x0099d802,
    0x0000d602,//20
    0x0000d702,
    0x00A1d802,
    0x00A5d802,
    0x00A1d802,
    0x00FFd602,//21
    0x0010d702,
    0x00A9d802,
    0x00ADd802,
    0x00A9d802,
    0x0000d602,//22
    0x00F0d702,
    0x00B1d802,
    0x00B5d802,
    0x00B1d802,
    0x0001d602,//23
    0x0068d702,
    0x00B9d802,
    0x00BDd802,
    0x00B9d802,
    0x0001d602,//24
    0x0068d702,
    0x00C1d802,
    0x00C5d802,
    0x00C1d802,
    0x0001d602,//25
    0x0068d702,
    0x00C9d802,
    0x00CDd802,
    0x00C9d802,
    0x0000d602,//26
    0x00F0d702,
    0x00D1d802,
    0x00D5d802,
    0x00D1d802,
    0x0000d602,//27
    0x00B4d702,
    0x00D9d802,
    0x00DDd802,
    0x00D9d802,
    0x00FFd602,//28
    0x004Cd702,
    0x00E1d802,
    0x00E5d802,
    0x00E1d802,
    0x00FFd602,//29
    0x00E2d702,
    0x00E9d802,
    0x00EDd802,
    0x00E9d802,
    0x0000d602,//30
    0x0000d702,
    0x00F1d802,
    0x00F5d802,
    0x00F1d802,
    0x0000d602,//31
    0x0000d702,
    0x00F9d802,
    0x00FDd802,
    0x00F9d802,
	#endif
//---------------------------		
    0x0001FF02,
    0x003e1e02,//-70
    0x00E81f02,//-70
		0x003f1e02,//-40
    0x00601f02,//-40
    0x0000FF02,
    0x0000FF12
		
//---------------------------		
};

const uint32_t init_pll_bw_cal[] = 
{
    0x0000ff02,
    
    0x02040202,
    0x14080A02,
    0xFF242D02,
    0x00042D02,
    0x00000A02,
    0x00100212,
};

/*const*/ uint32_t init_constant_tone[] =
{
    0x1A080002,
    0x24080a02,
    0x00480002,
    0x00947A02,  //modify by yangcheng 20210204
	
	0x00017402,
	
    0x201c7012,  // 0x25117012
};

uint32_t pre_tx_config_prf[] =
{
//	  0x0100d902,	/* bypass pre-emphasis */
//	  0x0101c602,	/* scale-0 */
//	  0x0100c702,	/* scale-1 */
//	  0x0100c802,	/* scale-2 */
    //0x012acc02,	/* gauss-filter */
#if MODE_1MBPS
    0x0F012802,
	0x01027E02,/**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
    0x00A0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
    0x0001bf02, /* iq-scale-delay =2.5us */
    0x0A080002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x24080a02, /**
                 * [7:4]: Reserved            = 0
                 * [3]  : fsyniqdivtxmode     = 1 (iqdiv-txdiv enable)
                 * [2]  : fsyniqdivrxmode     = 0 (iqdiv-rxdiv disable)
                 * [1]  : fsyniqdivfbdivmode  = 0 (Pll Fb-div clock: tx)
                 * [0]  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
    0x00480002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 1 (tx clock enable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x0F947A02, // PA, 0dBm
//    0x00147A02 | (CFG_RF_PHY_TX_POWER << 21), 
				 /**
                 * <7:5>: PA mode        = CFG_RF_PHY_TX_POWER
                 * <4>  : RX IQ switch   = 1
                 * <3>  : PA cap short   = 0 (slow ramp)
                 * <2>  : RX/Filter bias = 1 (high current)
                 * <1:0>: RXIF test mode = b00 (no input/output)
                 */
#endif
    //0x25117012
	0x0F1C7012	/**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 1 (PA CORE enable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b00
                 */
};

uint32_t pre_tx_config_2M_prf[] =
{
//	0x0100d902, /* bypass pre-emphasis */
//	0x0101c602, /* scale-0 */
//	0x0100c702, /* scale-1 */
//	0x0100c802, /* scale-2 */
//	0x012acc02, /* gauss-filter */
//0x000FC602,
#if MODE_2MBPS
    0x01012802,
    0x0A080002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */	
    0x01037E02, /**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
    0x00A0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
    0x0001bf02, /* iq-scale-delay =2.5us */
    0x24080a02, /**
                 * [7:4]: Reserved            = 0
                 * [3]  : fsyniqdivtxmode     = 1 (iqdiv-txdiv enable)
                 * [2]  : fsyniqdivrxmode     = 0 (iqdiv-rxdiv disable)
                 * [1]  : fsyniqdivfbdivmode  = 0 (Pll Fb-div clock: tx)
                 * [0]  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
    0x00480002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 1 (tx clock enable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x0F947A02, // PA, 0dBm
//    0x00147A02 | (CFG_RF_PHY_TX_POWER << 21), 
				 /**
                 * <7:5>: PA mode        = CFG_RF_PHY_TX_POWER
                 * <4>  : RX IQ switch   = 1
                 * <3>  : PA cap short   = 0 (slow ramp)
                 * <2>  : RX/Filter bias = 1 (high current)
                 * <1:0>: RXIF test mode = b00 (no input/output)
                 */
#endif
    //0x25117012
	0x0F1C7012 /**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 1 (PA CORE enable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b00
                 */
};

uint32_t pre_tx_config_LR[] =
{
//	0x0100d902, /* bypass pre-emphasis */
//	0x0101c602, /* scale-0 */
//	0x0100c702, /* scale-1 */
//	0x0100c802, /* scale-2 */
//	0x012acc02, /* gauss-filter */
#if MODE_LR
    0x0F012802,
   0x01027E02, /**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
    0x00E0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 1 (BLE long rang enable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	0x0001bf02,//iq-scale-delay =2.5us
    0x0A080002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x24080a02, /**
                 * [7:4]: Reserved            = 0
                 * [3]  : fsyniqdivtxmode     = 1 (iqdiv-txdiv enable)
                 * [2]  : fsyniqdivrxmode     = 0 (iqdiv-rxdiv disable)
                 * [1]  : fsyniqdivfbdivmode  = 0 (Pll Fb-div clock: tx)
                 * [0]  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
    0x00480002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 1 (tx clock enable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
	0x00207A02, // PA, 0dBm
//    0x00147A02 | (CFG_RF_PHY_TX_POWER << 21), 
				/**
                 * <7:5>: PA mode        = CFG_RF_PHY_TX_POWER
                 * <4>  : RX IQ switch   = 1
                 * <3>  : PA cap short   = 0 (slow ramp)
                 * <2>  : RX/Filter bias = 1 (high current)
                 * <1:0>: RXIF test mode = b00 (no input/output)
                 */
#endif
    //0x25117012
    0x0F1C7012  /**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 1 (PA CORE enable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b00
                 */
};

const uint32_t pre_tx_config_250K_prf[] =
{
	  // tri-angle  without  pre-emphasis
#if MODE_250KBPS
  	0x0140d902,/* bypass pre-emphasis */
    0x0103c602,/* scale-0 */
    0x0130c702,/* scale-1 */
    0x0100c802,/* scale-2 */
               
    0x01267E02,// [2] gauess_ovrd = 1   memory bank select   007e-default=0x22
    0x00A0C202,
    0x0001bf02,
    0x1A480002,
    0x24080a02,
    //0x00480002,
    0x00947A02, // PA, 0dBm
#endif
    //0x25117012
	0x201C7012
};


const uint32_t post_tx_config[] =
{
    0x00017002, /**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 0 (PA CORE disable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b00
                 */
    0x00147A02, /**
                 * <7:5>: PA mode        = b000 (off)
                 * <4>  : RX IQ switch   = 0
                 * <3>  : PA cap short   = 1 (fast ramp)
                 * <2>  : RX/Filter bias = 0 (low current)
                 * <1:0>: RXIF test mode = b01 (Mixer input/output)
                 */
    0x00002802,/* close pa &lna */
	0x00080012
                /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
};

const uint32_t pre_rx_config_prf[] =
{
	#if MODE_1MBPS

    0x01027E02, 	/*
                 * <7:5>: Reserved          = 0
								 * <5>  : 250KHz_mode = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
	 0x44022802,
	  //0x02402c02,
    0x00A0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
    
    0x0001BF02 ,

    0x00BFC302, /**
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 1 (DFE enable)
                 */
								 
    0x022C0002, /**
                 * <7>: scheme       = 0 (tx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 1 (rx clock enable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 1 (rx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    #endif
    0x1E060A12  /**
                 * <7:4>: Reserved            = 0
                 * <3>  : fsyniqdivtxmode     = 0 (iqdiv-txdiv disable)
                 * <2>  : fsyniqdivrxmode     = 1 (iqdiv-rxdiv enable)
                 * <1>  : fsyniqdivfbdivmode  = 1 (Pll Fb-div clock: rx)
                 * <0>  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
};

const uint32_t pre_rx_config_2M_prf[] =
{
	#if MODE_2MBPS
    
    0x01037E02, 	/*
                 * <7:5>: Reserved          = 0
								 * <5>  : 250KHz_mode = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 1 (1M PHY)
                 */
	  //0x02402c02,
	0x44022802,
    0x00A0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
    
    0x0001BF02 ,

    0x00BFC302, /**
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 1 (DFE enable)
                 */
								 
    0x022C0002, /**
                 * <7>: scheme       = 0 (tx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 1 (rx clock enable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 1 (rx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
		#endif
    0x1E060A12  /**
                 * <7:4>: Reserved            = 0
                 * <3>  : fsyniqdivtxmode     = 0 (iqdiv-txdiv disable)
                 * <2>  : fsyniqdivrxmode     = 1 (iqdiv-rxdiv enable)
                 * <1>  : fsyniqdivfbdivmode  = 1 (Pll Fb-div clock: rx)
                 * <0>  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
};

const uint32_t pre_rx_config_LR[] =
{
	#if MODE_LR
    0x44022802,
    0x00027E02, 	/*
                 * <7:5>: Reserved          = 0
								 * <5>  : 250KHz_mode = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
	  //0x02402c02,
    0x00E0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 1 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
    
    0x0001BF02 ,

    0x00BFC302, /**
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 1 (DFE enable)
                 */
								 
    0x022C0002, /**
                 * <7>: scheme       = 0 (tx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 1 (rx clock enable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 1 (rx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    #endif
    0x1E060A12  /**
                 * <7:4>: Reserved            = 0
                 * <3>  : fsyniqdivtxmode     = 0 (iqdiv-txdiv disable)
                 * <2>  : fsyniqdivrxmode     = 1 (iqdiv-rxdiv enable)
                 * <1>  : fsyniqdivfbdivmode  = 1 (Pll Fb-div clock: rx)
                 * <0>  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
};

const uint32_t pre_rx_config_250K_prf[] =
{
    #if MODE_2MBPS
    0x44022802,
	0x00207e02,
    0x02402c02,
	//0x00046002,
	#if BOE2
	0x01827E02, /**    BOE-MODEhaimeis*///[7]:BOE2_en
	0x00A8C202, /**    disable DFE
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 1
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	0x00BEC302, /**     disable DFE
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 0 (DFE enable)
                 */
  #else
  0x01227E02, /**    BOE-MODEhaimeis*/
                /* <7:5>: Reserved          = 0
								 * <5>  : 250KHz_mode = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
	 0x00A0C202, /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	 0x00BFC302, /**
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 1 (DFE enable)
                 */
	#endif

    
    0x0001BF02 ,
    0x022C0002, /**
                 * <7>: scheme       = 0 (tx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 1 (rx clock enable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 1 (rx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    #endif
    0x1E060A12  /**
                 * <7:4>: Reserved            = 0
                 * <3>  : fsyniqdivtxmode     = 0 (iqdiv-txdiv disable)
                 * <2>  : fsyniqdivrxmode     = 1 (iqdiv-rxdiv enable)
                 * <1>  : fsyniqdivfbdivmode  = 1 (Pll Fb-div clock: rx)
                 * <0>  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
};

const uint32_t post_rx_config[] =
{
    #if 0
	0x008FC312
    #endif
    0x00002802,//close pa &lna
    0x00080012
};

const uint32_t pre_evnt_config[] =
{
//    0x00845b02,
//    0x00845d02,
//    0x00805F02,
//    0x0A246E02,
//    0x05805A02,
    0x0A246E12
};

const uint32_t post_evnt_config[] =
{
    0x00000A02,
    0x00000012,
};

uint32_t channel_initialize[] =
{
	0x01007D12
};


const uint32_t init_sleep_size                  = sizeof init_sleep;
const uint32_t init_stdby_config_size           = sizeof init_stdby_config;
const uint32_t init_slp_to_stdby_config_size    = sizeof init_slp_to_stdby_config;
const uint32_t pwr_reset_size                   = sizeof pwr_reset;
const uint32_t phy_init_size                    = sizeof phy_init;
const uint32_t pre_tx_config_prf_size           = sizeof pre_tx_config_prf;
const uint32_t pre_tx_config_LR_size            = sizeof pre_tx_config_LR;

const uint32_t pre_tx_config_2M_prf_size        = sizeof pre_tx_config_2M_prf;
const uint32_t pre_tx_config_250K_prf_size      = sizeof pre_tx_config_250K_prf;
const uint32_t post_tx_config_size              = sizeof post_tx_config;
const uint32_t pre_rx_config_prf_size           = sizeof pre_rx_config_prf;
const uint32_t pre_rx_config_LR_size            = sizeof pre_rx_config_LR;
const uint32_t pre_rx_config_2M_prf_size        = sizeof pre_rx_config_2M_prf;
const uint32_t pre_rx_config_250K_prf_size      = sizeof pre_rx_config_250K_prf;
const uint32_t post_rx_config_size              = sizeof post_rx_config;
const uint32_t pre_evnt_config_size             = sizeof pre_evnt_config;
const uint32_t post_evnt_config_size            = sizeof post_evnt_config;
const uint32_t channel_initialize_size          = sizeof channel_initialize;

const uint32_t init_constant_tone_size          = sizeof init_constant_tone;

const uint32_t init_pll_bw_cal_size             = sizeof init_pll_bw_cal;

const uint8_t phy_chan_cfg_reg                    = 0x7D;
const uint8_t phy_rssi_out_reg_adr                = 0x85;

uint8_t phy_set_time_cfg_prf(uint8_t phy, uint8_t tx1rx0)   /*most time is 101us*/
{
	uint8_t ret = 0;
	
	if(phy == 1)  //2m
	{
		if(tx1rx0 == 1)//tx
		{
			for (uint8_t i=0; i<(post_tx_config_size>>2);i++)
			{
				ret += ((post_tx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_rx_config_2M_prf_size>>2);i++)
			{
				ret += ((pre_rx_config_2M_prf[i] & 0xFF000000) >> 24);
			}
		}
		else     //rx
		{
			for (uint8_t i=0; i<(post_rx_config_size>>2);i++)
			{
				ret += ((post_rx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_tx_config_2M_prf_size>>2);i++)
			{
				ret += ((pre_tx_config_2M_prf[i] & 0xFF000000) >> 24);
			}
		}
	}
	else  //1m
	{
		if(tx1rx0==1)//tx
		{
			for (uint8_t i=0; i<(post_tx_config_size>>2);i++)
			{
				ret += ((post_tx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_rx_config_prf_size>>2);i++)
			{
				ret += ((pre_rx_config_prf[i] & 0xFF000000) >> 24);
			}
		}
		else     //rx
		{
			for (uint8_t i=0; i<(post_rx_config_size>>2);i++)
			{
				ret += ((post_rx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_tx_config_prf_size>>2);i++)
			{
				ret += ((pre_tx_config_prf[i] & 0xFF000000) >> 24);
			}
		}
	}
	return ret;
}

static inline void PHY_FifoFlush(void)
{
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FLUSH, 0x1);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FLUSH, 0x0);

	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_FLUSH, 0x1);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_FLUSH, 0x0);
}

__ramfunc uint32_t PHY_WriteCfgFifoBatch(const uint32_t *command, const uint32_t cmd_len, uint32_t *ptr_rsp_value)
{
	volatile uint32_t reg = 0;
	uint32_t time_out = 0, cmd_idx = 0;
	uint32_t rsp_len = 0;

	if (0 == cmd_len) {
		goto fun_ext;
	}

	/* Flush the PHY Driver FIFO */
	PHY_FifoFlush();

	/* Trigger the FIFO */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_TRG, 0x1);

	do {
			do {
					/* check that the FIFO is empty */
					reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_BUF_FULL);
			} while (reg == 1);

			/* Write the commands to FIFO */
			PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY3, PHY_DRV_CFG_BUF_DIN, command[cmd_idx++]);

			/* check that the Response buff is full */
			reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);
			if ((ptr_rsp_value != NULL) && (reg == 0)) {
					/* read the response from FIFO */
					ptr_rsp_value[rsp_len++] = PRI_RF_READ_REG_VALUE(PRI_RF, PHY4, PHY_DRV_RSP_BUF_DOUT);
			}
	} while (cmd_idx < cmd_len);

	do {
			time_out++;
			reg = PRI_RF_READ_REG_VALUE(PRI_RF, INTR1, IC_PHY_DRV_CFG_DONE);
	} while (reg == 0 && time_out < 255);

	if (time_out == 255)
	{
		goto fun_ext;
	}

	/* check that the Response buff is full */
	reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSP_BUF_EMPTY);

	while ((ptr_rsp_value != NULL) && (reg == 0)) {
			/* read the response from FIFO */
			ptr_rsp_value[rsp_len++] = PRI_RF_READ_REG_VALUE(PRI_RF, PHY4, PHY_DRV_RSP_BUF_DOUT);
			/* check that the Response buff is full */
			reg = PRI_RF_READ_REG_VALUE(PRI_RF, PHY1,  PHY_DRV_RSP_BUF_EMPTY);
	}

	/* Clear the interrupt */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, INTCLR, IC_PHY_DRV_CFG_DONE_CLR, 1);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, INTCLR, IC_PHY_DRV_CFG_DONE_CLR, 0);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_TRG, 0x0);

fun_ext:
	return rsp_len;
}

void PHY_reset(void)
{
    PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, IF_CLK_PRESCALE, 2);
	/* select PHY scheme */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_CFG_REG, 0);
	PHY_WriteCfgFifoBatch(pwr_reset, (pwr_reset_size >> 2), NULL);
}


__ramfunc uint32_t PHY_SeqRamInit(void)
{
	uint32_t j = 0;
	uint32_t seq_ram_index = 0;

	seq_ram_index  = SEQ_RAM_OFST ;
	for (j = 0; j < (post_tx_config_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, post_tx_config[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (post_rx_config_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, post_rx_config[j]);
			seq_ram_index += 4;
	}

	for (j = 0; j < (pre_tx_config_prf_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config_prf[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_tx_config_2M_prf_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config_2M_prf[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_tx_config_LR_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config_LR[j]);
			seq_ram_index += 4;
	}

	for (j = 0; j < (pre_rx_config_prf_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config_prf[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_rx_config_2M_prf_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config_2M_prf[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_rx_config_LR_size >> 2); j++)
	{
			LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config_LR[j]);
			seq_ram_index += 4;
	}
	for (j = 0; j < (pre_tx_config_250K_prf_size >> 2); j++)
    {
        LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_tx_config_250K_prf[j]);
        seq_ram_index += 4;
    }
	for (j = 0; j < (pre_rx_config_250K_prf_size >> 2); j++)
    {
        LLHWC_WRITE32_REG(REG_FILE_OFST, seq_ram_index, pre_rx_config_250K_prf[j]);
        seq_ram_index += 4;
    }	
	
	return seq_ram_index;
}

void PHY_SetChConfig(uint8_t chan)
{
	channel_initialize[0] = (channel_initialize[0] & 0xFF00FFFF) | (((0x000000FF & (uint32_t)chan)) << 16);
	PHY_WriteCfgFifoBatch(channel_initialize, (channel_initialize_size >> 2), NULL);
}

__ramfunc void PHY_strt_stp(llhw_phy_strt_stp_phy_e phy_state)
{
  if (LLHWC_PHY_START == phy_state)
  {
        ana_prf_ldo_en();
  }
  else
  {
        ana_prf_ldo_dis();
  }
}

void PHY_init(void)
{
	uint32_t tmp;

	if (PHY_SeqRamInit() >= SEQ_RAM_OFST + 512) {
		return;
	}

	tmp = PHY_WriteCfgFifoBatch(phy_init, (phy_init_size >> 2), NULL);
	tmp = PHY_WriteCfgFifoBatch(init_sleep, (init_sleep_size >> 2), NULL);

	/* This field specifies the Sequencer start address for TX end operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_END_ADDR, 0);
	/* This field specifies the Sequencer start address for RX end operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_END_ADDR, (post_tx_config_size >> 2));
	/* Write the address of the RSSI register in the PHY register file so as to the link layer read it
	* and append it to the end of the packet received */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY1, PHY_DRV_RSSI_REG_ADDR, phy_rssi_out_reg_adr);
	/* selecting the new PHY used in Version 5.0 by setting the channel register by 7D*/
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY5, PHY_DRV_SET_CHAN_REG_ADDR, phy_chan_cfg_reg);
}

__ramfunc void PHY_ResetChannel(void)
{
    uint32_t cmd_channel[] = {
        0x001B5602,
        0x0008B302,
        0x0000B402,
        0x0000B502,
        0x0000BE02,
        0x0000B602,
		0x0010B702,
        0x0000B812,
    };
    
    PHY_WriteCfgFifoBatch(cmd_channel, (sizeof cmd_channel >> 2), NULL);
}

__ramfunc void PHY_SetExternChannel(uint16_t rf_channel, uint8_t calibrate, uint8_t phy)
{
    uint32_t cmd_channel[] = {
        0x00805602,
        0x000CB302,
        0x0000B402,
        0x0000B502,
        0x0000BE02,
        0x0000B602,
		0x0000B702,
        0x0000B812,
    };
    
	uint8_t  tmp_int_part ;
	uint8_t  divider_ratio;//freq_int_part
    int32_t  tmp_frac_part; 
    uint32_t offset       ;//freq_frac_part
		
    tmp_int_part  = rf_channel - (rf_channel/32)*32;
	divider_ratio = (tmp_int_part>=16) ? rf_channel/32 -32  + 1  :  rf_channel/32 -32 ;
	tmp_frac_part = (tmp_int_part>=16) ? tmp_int_part - 32 : tmp_int_part ;
	offset        = (tmp_frac_part>0) ? tmp_frac_part*4096 : 262144 + tmp_frac_part*4096 ; 
 
    cmd_channel[0] |= (divider_ratio << 16);
    cmd_channel[1] |= (((offset >> 16) & 0x03) << 16);
    cmd_channel[2] |= (((offset >>  8) & 0xFF) << 16);
    cmd_channel[3] |= (((offset >>  0) & 0xFF) << 16);
	
	rf_channel    = rf_channel - phy;
	tmp_int_part  = rf_channel - (rf_channel/32)*32;
	divider_ratio = (tmp_int_part>=16) ? rf_channel/32 -32  + 1  :  rf_channel/32 -32 ;
	tmp_frac_part = (tmp_int_part>=16) ? tmp_int_part - 32 : tmp_int_part ;
	offset        = (tmp_frac_part>0) ? tmp_frac_part*4096 : 262144 + tmp_frac_part*4096 ; 	

	cmd_channel[4] |= (divider_ratio << 16);
    cmd_channel[5] |= (((offset >> 16) & 0x03) << 16);
    cmd_channel[6] |= (((offset >>  8) & 0xFF) << 16);
    cmd_channel[7] |= (((offset >>  0) & 0xFF) << 16);

    PHY_WriteCfgFifoBatch(cmd_channel, (sizeof cmd_channel >> 2), NULL);

    if (1 == calibrate) {
		ana_prf_ldo_en();
    	
        const uint32_t init_vco_cal[] =
        {
            0x0000ff02,
            
            0x02080202,
            0x64080A02,
            0xff980302,
            0x00900302,
            0x00000A02,
            0x00000212			
        };
        // vco Calibration
        PHY_WriteCfgFifoBatch(init_vco_cal, (sizeof init_vco_cal >> 2), NULL);
        
        const uint32_t init_pll_bw_cal[] = 
        {
            0x0000FF02,
            
            0x02040202,
            0x14080A02,
            
            0xFF222D02,
            0x00022D02,
            
            0x00000A02,
            0x00000212,
        };
        // PLL-BW Calibration
        PHY_WriteCfgFifoBatch(init_pll_bw_cal, (sizeof init_pll_bw_cal >> 2), NULL);

        ana_prf_ldo_dis();
    } else {
        uint32_t init_channel[] = {
            0x01007D12,
        };

        uint8_t ch_idx = (rf_channel + phy) - 2400;

        if(ch_idx % 2)
        {
            ch_idx = ch_idx / 2 ;
        }
        else
        {
            ch_idx = ch_idx / 2 - 1;
        }
        init_channel[0] |= (ch_idx << 16);
        PHY_WriteCfgFifoBatch(init_channel, (sizeof init_channel >> 2), NULL);
    }
}

void PHY_SetTrxSeq_prf(enum tx_rx_phy phy) 
{
	uint32_t txseq_ram_index = 0;
    uint32_t rxseq_ram_index = 0;

    txseq_ram_index = (post_tx_config_size >> 2)
                    + (post_rx_config_size >> 2);                
    rxseq_ram_index = (post_tx_config_size >> 2)
                    + (post_rx_config_size >> 2)
                    + (pre_tx_config_prf_size >> 2)
                    + (pre_tx_config_2M_prf_size >> 2)
                    + (pre_tx_config_LR_size >> 2);
    if(LE_1M == phy) {
		PRI_RF_WRITE_REG_VALUE(PRI_RF, R00_CTL, BW_MODE, 0);  //0 1M; 1 2m
	} else if (LE_2M == phy) {
        txseq_ram_index = txseq_ram_index + (pre_tx_config_prf_size >> 2);
        rxseq_ram_index = rxseq_ram_index + (pre_rx_config_prf_size >> 2);
		PRI_RF_WRITE_REG_VALUE(PRI_RF, R00_CTL, BW_MODE, 1);  //0 1M; 1 2m
    }
	else if(LE_250K == phy) {
		txseq_ram_index = rxseq_ram_index + (pre_rx_config_prf_size >> 2) + (pre_rx_config_2M_prf_size >> 2)
						+ (pre_rx_config_LR_size >> 2);
		rxseq_ram_index = txseq_ram_index + (pre_tx_config_250K_prf_size >> 2);
		
		PRI_RF_WRITE_REG_VALUE(PRI_RF, R11_CFG, BOE_MODE, ENABLE);
	}
	else if((LE_CODED_S8 == phy) || (LE_CODED == phy)) {
		txseq_ram_index = txseq_ram_index + (pre_tx_config_prf_size >> 2) + (pre_tx_config_2M_prf_size >> 2);
		rxseq_ram_index = rxseq_ram_index + (pre_rx_config_prf_size >> 2) + (pre_rx_config_2M_prf_size >> 2);
		
		if(LE_CODED_S8 == phy)
		{
			PRI_RF_WRITE_REG_VALUE(PRI_RF, R04_RX_CTL, CI_MODE, 0);
		}
		else if(LE_CODED == phy)
		{
			PRI_RF_WRITE_REG_VALUE(PRI_RF, R04_RX_CTL, CI_MODE, 1);
		}
	}

    /* This field specifies the Sequencer start address for TX start operation sequence. */
    PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_STRT_ADDR, txseq_ram_index);
    PRI_RF_WRITE_REG_VALUE(PRI_RF,PHY2, PHY_DRV_SEQ_TX_END_ADDR, 0);                
    /* This field specifies the Sequencer start address for RX start operation sequence. */
    PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_STRT_ADDR, rxseq_ram_index);
    PRI_RF_WRITE_REG_VALUE(PRI_RF,PHY2, PHY_DRV_SEQ_RX_END_ADDR, (post_tx_config_size >> 2)); 
}

typedef struct {
    uint8_t  pa_mode; //      R007A[ 5:3]
    uint8_t  pa_bias; //      R0057[ 4:0]
    uint16_t pa_ramp; // 0x40030048[15:6]
} tx_pwr_val_t;

const static tx_pwr_val_t tx_pwr_val[] = 
{
    { 0x01, 0x10, 0x03FF }, // -45 dBm
    { 0x01, 0x11, 0x003F }, // -44 dBm
    { 0x01, 0x11, 0x00FF }, // -43 dBm
    { 0x01, 0x11, 0x03FF }, // -42 dBm, need update
    { 0x01, 0x12, 0x0000 }, // -41 dBm, need update
    { 0x01, 0x12, 0x0003 }, // -40 dBm
    { 0x03, 0x00, 0x0000 }, // -39 dBm
    { 0x03, 0x00, 0x0001 }, // -38 dBm
    { 0x03, 0x00, 0x0001 }, // -37 dBm, need update
    { 0x03, 0x00, 0x0003 }, // -36 dBm, need update
    { 0x03, 0x00, 0x0003 }, // -35 dBm
    { 0x03, 0x00, 0x000F }, // -34 dBm
    { 0x03, 0x00, 0x001F }, // -33 dBm
    { 0x03, 0x00, 0x007F }, // -32 dBm
    { 0x03, 0x00, 0x00FF }, // -31 dBm
    { 0x03, 0x02, 0x0000 }, // -30 dBm, need update
    { 0x03, 0x03, 0x0000 }, // -29 dBm
    { 0x03, 0x03, 0x0001 }, // -28 dBm, need update
    { 0x03, 0x04, 0x0000 }, // -27 dBm
    { 0x03, 0x05, 0x0001 }, // -26 dBm, need update
    { 0x03, 0x05, 0x0000 }, // -25 dBm
    { 0x03, 0x06, 0x0000 }, // -24 dBm
    { 0x03, 0x07, 0x0000 }, // -23 dBm
    { 0x03, 0x08, 0x0000 }, // -22 dBm
    { 0x03, 0x09, 0x0000 }, // -21 dBm
    { 0x03, 0x0A, 0x0000 }, // -20 dBm
    { 0x03, 0x0B, 0x0000 }, // -19 dBm
    { 0x03, 0x0D, 0x0000 }, // -18 dBm
    { 0x03, 0x0F, 0x0000 }, // -17 dBm
    { 0x03, 0x05, 0x0001 }, // -16 dBm
    { 0x03, 0x05, 0x000F }, // -15 dBm, need update
    { 0x03, 0x06, 0x0001 }, // -14 dBm
    { 0x03, 0x07, 0x0001 }, // -13 dBm
    { 0x03, 0x07, 0x000F }, // -12 dBm, need update
    { 0x03, 0x08, 0x0001 }, // -11 dBm
    { 0x03, 0x09, 0x0001 }, // -10 dBm
    { 0x03, 0x09, 0x000F }, //  -9 dBm, need update
    { 0x03, 0x0A, 0x0001 }, //  -8 dBm
    { 0x03, 0x0B, 0x0001 }, //  -7 dBm
    { 0x03, 0x0C, 0x0001 }, //  -6 dBm
    { 0x03, 0x0D, 0x0001 }, //  -5 dBm
    { 0x03, 0x0E, 0x0001 }, //  -4 dBm
    { 0x01, 0x0F, 0x0003 }, //  -3 dBm
    { 0x01, 0x0F, 0x001F }, //  -2 dBm
    { 0x01, 0x0F, 0x03FF }, //  -1 dBm
    { 0x03, 0x0B, 0x0003 }, //   0 dBm
    { 0x03, 0x0C, 0x0003 }, //   1 dBm
    { 0x03, 0x0D, 0x0003 }, //   2 dBm
    { 0x03, 0x0E, 0x0007 }, //   3 dBm
    { 0x03, 0x0E, 0x00FF }, //   4 dBm
    { 0x04, 0x0A, 0x00FF }, //   5 dBm
    { 0x04, 0x0F, 0x00FF }, //   6 dBm
    { 0x04, 0x0F, 0x03FF }, //   7 dBm
};

/**
 * @brief  Set the TX Power value.
 *
 * @param  tx_pwr: [in] TX power value to be used by the controller.
 *
 * @retval ble_stat_t : Command status to be sent to the Host.
 */
__ramfunc void PHY_set_tx_pwr(int8_t tx_pwr)
{
#define MIN_SPPRTD_TX_POWER         -45         /* Minimum transmit power supported by the PHY [unit: dBm] */
#define MAX_SPPRTD_TX_POWER         7           /* Maximum transmit power supported by the PHY [unit: dBm] */

    uint32_t config_pa_mode;
    uint32_t config_pa_bias = 0x00005712;
    uint32_t config_pa_ramp = 0;

    if((tx_pwr > 7) && (tx_pwr < -45)) {
        return;
    }
    tx_pwr -= MIN_SPPRTD_TX_POWER;
    config_pa_ramp = tx_pwr_val[tx_pwr].pa_ramp << 6;

    MODIFY_REG(SYS->CTRL0, 0xFFC0, config_pa_ramp);

    config_pa_bias |= (tx_pwr_val[tx_pwr].pa_bias << 16);
    PHY_WriteCfgFifoBatch(&config_pa_bias, 1, NULL);

    config_pa_mode = ((pre_tx_config_prf[pre_tx_config_prf_size/4-2] & 0xFF1FFFFF) | (tx_pwr_val[tx_pwr].pa_mode << 21));
    pre_tx_config_prf[pre_tx_config_prf_size/4-2]       = config_pa_mode;
    pre_tx_config_LR[pre_tx_config_LR_size/4-2] = config_pa_mode;
    pre_tx_config_2M_prf[pre_tx_config_2M_prf_size/4-2] = config_pa_mode;

    PHY_SeqRamInit();
}

void panchip_prf_dev_set(prf_dev_sel_t dev)
{	
	if(dev == PRF_DEV_BLE)				//ble dev  1M,250k
	{
		uint32_t value_nrf[4] = {
 			0x0057DE02,//eq-coeff eq-th 3.5/4.9		//rx
 			0x0009C102,//[3:0]fb_coeff 6.3
 			0x0078D302,//[7:3]ff_coeff 10.5
 			0x0005DF12,//ffe-th 3.5
 		};
		
		PHY_WriteCfgFifoBatch(value_nrf, (sizeof value_nrf >> 2), NULL);
	}
	else if(dev == PRF_DEV_NRF)			//nrf dev  1M,170k
	{
		uint32_t value_nrf[4] = {
 			0x0035DE02,//eq-coeff eq-th 3.5/4.9		//rx
 			0x0006C102,//[3:0]fb_coeff 6.3
 			0x0051D302,//[7:3]ff_coeff 10.5
 			0x0004DF12,//ffe-th 3.5
 		};
		
		PHY_WriteCfgFifoBatch(value_nrf, (sizeof value_nrf >> 2), NULL);
	}
}


void panchip_prf_carrier_start(uint16_t  tx_channel)
{
    const uint32_t init_constant_tone[] = {
        0x1A080002,
        0x24080A02,
        0x00480002,
        0x00947A02,
        0x201C7012,
    };

	PHY_SetExternChannel(tx_channel, 1, 1);

	ana_prf_ldo_en();

	PHY_WriteCfgFifoBatch(init_constant_tone, (sizeof(init_constant_tone) >> 2), NULL);
}

void panchip_prf_carrier_stop(void)
{
    const uint32_t tx_end_config[] = {
        0x1A0E7002,
        0x00147A02,
        0x00080012,
    };

	PHY_WriteCfgFifoBatch(tx_end_config, (sizeof(tx_end_config) >> 2), NULL);
}

uint8_t read_rssi_flag = 0;
void panchip_prf_enable_rssi(void)
{
	uint32_t value = 0x00019512;
	
	PHY_WriteCfgFifoBatch(&value, (sizeof value >> 2), NULL);
    read_rssi_flag = 1;
}

void panchip_prf_disable_rssi(void)
{
	uint32_t value[] = {
        0x00099502,
        0x0013F512,
    };
	
	PHY_WriteCfgFifoBatch(value, (sizeof(value) >> 2), NULL);
    read_rssi_flag = 0;
}

int16_t panchip_prf_read_rssi(void)
{
	uint32_t response;
    uint32_t rssi;
    int16_t rssi_db;

    uint32_t ed_cmd[] = {
        0x00008613, // rssi-out bit[7-0]
        0x00008513, // rssi-out bit[12-8]
    }; 
        
    PHY_WriteCfgFifoBatch(&ed_cmd[1], 1, &response);
    rssi = (response & 0x3F) << 8;
    
    PHY_WriteCfgFifoBatch(&ed_cmd[0], 1, &response);
    rssi += response & 0xFF;

    rssi_db = ((int16_t)rssi-16384)/4;
    
    return rssi_db;
}

uint8_t read_carrier_rssi_flag = 0;
int16_t panchip_prf_enable_carrier_rssi(void)
{
    uint32_t value[] = {
        0x00019502,
        0x0000f112,
    };
	
    panchip_prf_rx_stop();
	PHY_WriteCfgFifoBatch(value, (sizeof value >> 2), NULL);
    panchip_prf_trx_start();

    read_carrier_rssi_flag = 1;
}

void panchip_prf_disable_carrier_rssi(void)
{
	uint32_t value[] = {
        0x00099502,
        0x0013F502,
        0x000df112,
    };
	
	PHY_WriteCfgFifoBatch(value, (sizeof(value) >> 2), NULL);

    read_carrier_rssi_flag = 0;
}

int16_t panchip_prf_read_carrier_rssi(void)
{
    uint32_t response;
    uint32_t rssi;
    int16_t rssi_db;
    int32_t  rssi_avg = 0;

    uint32_t ed_cmd[] = {
        0x00042b12, // 0 enable rssi read mode 
        0x0000b013, // 1 read rssi value [13:8] bits
        0x0000b113, // 2 read rssi value [7:0] bits
        0x00002b12, // 3 disable rssi read mode        
    }; 

    if (read_carrier_rssi_flag == 0) 
    {
        return 0;
    }
        
    PHY_WriteCfgFifoBatch(&ed_cmd[0], 1, NULL);

    for (int i = 0; i<500;i++)
	{
        PHY_WriteCfgFifoBatch(&ed_cmd[1], 1, &response);
        rssi = (response & 0x3F) << 8;
        
        PHY_WriteCfgFifoBatch(&ed_cmd[2], 1, &response);
        rssi += response & 0xFF;

        rssi_db = ((int16_t)rssi-16384)/4;

        rssi_avg += rssi_db;
    }
	
    PHY_WriteCfgFifoBatch(&ed_cmd[3], 1, NULL);

    rssi_db = rssi_avg / 500;
    return rssi_db;
}

void panchip_prf_dev_650k(void)
{
    uint32_t value[] = {
		0x0001C602,
		0x004CC702,
		0x00CDC812,
	};

	PHY_WriteCfgFifoBatch(value, (sizeof(value) >> 2), NULL);
}

#if 0
uint32_t pre_tx_config_dual[] =
{
    0x01027E02, /**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
    0x00A0C202, 
                /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	0x000ABF02,//iq-scale-delay =2.5us
    0x1A080002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x24080A02, /**
                 * [7:4]: Reserved            = 0
                 * [3]  : fsyniqdivtxmode     = 1 (iqdiv-txdiv enable)
                 * [2]  : fsyniqdivrxmode     = 0 (iqdiv-rxdiv disable)
                 * [1]  : fsyniqdivfbdivmode  = 0 (Pll Fb-div clock: tx)
                 * [0]  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
    0x00480002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 1 (tx clock enable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x00147A02 | (CFG_RF_PHY_TX_POWER << 21), /**
                 * <7:5>: PA mode        = CFG_RF_PHY_TX_POWER
                 * <4>  : RX IQ switch   = 1
                 * <3>  : PA cap short   = 0 (slow ramp)
                 * <2>  : RX/Filter bias = 1 (high current)
                 * <1:0>: RXIF test mode = b00 (no input/output)
                 */
    0x201C7012  /**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 1 (PA CORE enable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b00
                 */
};

uint32_t pre_tx_config_2M_dual[] =
{
    0x00037E02, /**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 1 (2M PHY)
                 */
    0x00A0C202, 
                /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	0x000ABF02,//iq-scale-delay =2.5us
    0x1A080002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x26080A02, /**
                 * [7:4]: Reserved            = 0
                 * [3]  : fsyniqdivtxmode     = 1 (iqdiv-txdiv enable)
                 * [2]  : fsyniqdivrxmode     = 0 (iqdiv-rxdiv disable)
                 * [1]  : fsyniqdivfbdivmode  = 0 (Pll Fb-div clock: tx)
                 * [0]  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
    0x00480002, /**
                 * <7>: scheme       = 0 (rx scheme)
                 * <6>: txtopen      = 1 (tx clock enable)
                 * <5>: rxtopen      = 0 (rx clock disable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 0 (tx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x00147A02 | (CFG_RF_PHY_TX_POWER << 21), /**
                 * <7:5>: PA mode        = CFG_RF_PHY_TX_POWER
                 * <4>  : RX IQ switch   = 1
                 * <3>  : PA cap short   = 0 (slow ramp)
                 * <2>  : RX/Filter bias = 1 (high current)
                 * <1:0>: RXIF test mode = b00 (no input/output)
                 */
    0x201C7012  /**
                 * <7:5>: Reserved        = 0
                 * <4>  : txpaen          = 1 (PA CORE enable)
                 * <3:2>: rfmtchntwkc1val = b11
                 * <1:0>: rfmtchntwkc2val = b00
                 */
};

const uint32_t pre_rx_config_dual[] =
{
    0x01027E02, /**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 0 (1M PHY)
                 */
    0x00A0C202, 
                /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	0x000ABF02,//iq-scale-delay =2.5us
    0x00bfC302, /**  3e
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 1 (DFE enable)
                 */
    0x022C0002, /**
                 * <7>: scheme       = 0 (tx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 1 (rx clock enable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 1 (rx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x1E060A12  /**
                 * <7:4>: Reserved            = 0
                 * <3>  : fsyniqdivtxmode     = 0 (iqdiv-txdiv disable)
                 * <2>  : fsyniqdivrxmode     = 1 (iqdiv-rxdiv enable)
                 * <1>  : fsyniqdivfbdivmode  = 1 (Pll Fb-div clock: rx)
                 * <0>  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
};

const uint32_t pre_rx_config_2M_dual[] =
{
    0x00004D02, /**
                 * ?????
                 */
    0x01037E02, /**
                 * <7:5>: Reserved          = 0
                 * <4>  : preemch_coeff_sel = 0
                 * <3>  : gauss_bt          = 0 (bt = 0.5)
                 * <2>  : gauss_ovrd        = 0
                 * <1>  : tx_osr            = 1
                 * <0>  : bitrate           = 1 (2M PHY)
                 */
    0x00A0C202, 
                /**
                 * <7>  : en_drift_compensate = 1 (Drift Compensate enable)
                 * <6>  : ble_long_range      = 0 (BLE long rang disable)
                 * <5>  : en_off_est_timeout  = 1 (offset-estimation timeout function enable)
                 * <4>  : gate_soft_bits      = 0
                 * <3>  : dfe_en_ovrd         = 0
                 * <2>  : agg_cdr_ovrd        = 0
                 * <1>  : demod_en_wide_bw    = 0
                 * <0>  : Reserved            = 0
                 */
	0x000ABF02,//iq-scale-delay =2.5us
    0x00BFC302, /**
                 * <7>  : en_cdr              = 1 (Clock data recovery enable)
                 * <6>  : en_cdr_in_acc_match = 0 (Clock data recovery in access address match disable)
                 * <5>  : idataouten          = 1 (output_i: rx_clk)
                 * <4>  : qdataouten          = 1 (output_i: rx_data)
                 * <3>  : rxbit_dataout_sel   = 1 (data-i after mixer)
                 * <2>  : oqpsk_lsb_1st       = 1 (Working in Zigbee mode)????????????????????????????????????????????????????
                 * <1>  : use_quad_mixer      = 1 (mixer enable)
                 * <0>  : en_dfe              = 1 (DFE enable)
                 */
    0x022C0002, /**
                 * <7>: scheme       = 0 (tx scheme)
                 * <6>: txtopen      = 0 (tx clock disable)
                 * <5>: rxtopen      = 1 (rx clock enable)
                 * <4>: biastopen    = 0 (bias clock disable)
                 * <3>: fsyntopen    = 1 (pll clock enable)
                 * <2>: rxtx_mode    = 1 (rx)
                 * <1>: Reserved     = 0
                 * <0>: fsynxobuffen = 0 (xo output buffer disable)
                 */
    0x1E060A12  /**
                 * <7:4>: Reserved            = 0
                 * <3>  : fsyniqdivtxmode     = 0 (iqdiv-txdiv disable)
                 * <2>  : fsyniqdivrxmode     = 1 (iqdiv-rxdiv enable)
                 * <1>  : fsyniqdivfbdivmode  = 1 (Pll Fb-div clock: rx)
                 * <0>  : fsyniqdivcaldivmode = 0 (Pll Cal-div clock: tx)
                 */
};

const uint32_t pre_tx_config_dual_size          = sizeof pre_tx_config_dual;
const uint32_t pre_tx_config_2M_dual_size       = sizeof pre_tx_config_2M_dual;
const uint32_t pre_rx_config_dual_size          = sizeof pre_rx_config_dual;
const uint32_t pre_rx_config_2M_dual_size       = sizeof pre_rx_config_2M_dual;

uint8_t phy_set_time_cfg_dual(uint8_t phy, uint8_t tx1rx0)   /*most time is 101us*/
{
	uint8_t ret = 0;
	
	if(phy == 1)  //2m
	{
		if(tx1rx0 == 1)//tx
		{
			for (uint8_t i=0; i<(post_tx_config_size>>2);i++)
			{
				ret += ((post_tx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_rx_config_2M_dual_size>>2);i++)
			{
				ret += ((pre_rx_config_2M_dual[i] & 0xFF000000) >> 24);
			}
		}
		else     //rx
		{
			for (uint8_t i=0; i<(post_rx_config_size>>2);i++)
			{
				ret += ((post_rx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_tx_config_2M_dual_size>>2);i++)
			{
				ret += ((pre_tx_config_2M_dual[i] & 0xFF000000) >> 24);
			}
		}
	}
	else  //1m
	{
		if(tx1rx0==1)//tx
		{
			for (uint8_t i=0; i<(post_tx_config_size>>2);i++)
			{
				ret += ((post_tx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_rx_config_dual_size>>2);i++)
			{
				ret += ((pre_rx_config_dual[i] & 0xFF000000) >> 24);
			}
		}
		else     //rx
		{
			for (uint8_t i=0; i<(post_rx_config_size>>2);i++)
			{
				ret += ((post_rx_config[i] & 0xFF000000) >> 24);
			}
			for (uint8_t i=0; i<(pre_tx_config_dual_size>>2);i++)
			{
				ret += ((pre_tx_config_dual[i] & 0xFF000000) >> 24);
			}
		}
	}
	return ret;
}

void PHY_SetTrxSeq_dual(enum tx_rx_phy phy) 
{                
	uint32_t txseq_ram_index = 0;
	uint32_t rxseq_ram_index = 0;

	txseq_ram_index = (post_tx_config_size >> 2)
									+ (post_rx_config_size >> 2);                
	rxseq_ram_index = (post_tx_config_size >> 2)
									+ (post_rx_config_size >> 2)
									+ (pre_tx_config_dual_size >> 2)
									+ (pre_tx_config_2M_dual_size >> 2)
									+ (pre_tx_config_LR_size >> 2);
	
	if (LE_2M == phy)
	{
		txseq_ram_index = txseq_ram_index + (pre_tx_config_dual_size >> 2);
		rxseq_ram_index = rxseq_ram_index + (pre_rx_config_dual_size >> 2);
	}

	/* This field specifies the Sequencer start address for TX start operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_STRT_ADDR, txseq_ram_index);
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_TX_END_ADDR, 0);
	/* This field specifies the Sequencer start address for RX start operation sequence. */
	PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_STRT_ADDR, rxseq_ram_index);
	// PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_END_ADDR, 2); 
    PRI_RF_WRITE_REG_VALUE(PRI_RF, PHY2, PHY_DRV_SEQ_RX_END_ADDR, (post_tx_config_size >> 2));
}
#endif


#endif





/*** (C) COPYRIGHT 2020 Panchip Technology Corp. ***/
